1. Field of the Invention
The present disclosure relates to image sensing, and more particularly, to circuits and methods for sub-sampling of image sensing devices.
2. Description of the Related Art
A Charge-Coupled Device (CCD) has been used as the most popular solid state image sensing device. With the growth of the semiconductor industry, the CCD has been rapidly developed and eventually applied to high-performance small cameras. Although the CCD is an important image pick-up device, a CCD sensor, a core element of a digital camera, consumes relatively large amounts of energy and is not suitable for high-speed operation. Accordingly, a CMOS Image Sensor (CIS) capable of realizing high resolution of more than hundreds of pixels has been developed. The CIS can be highly integrated such that a very large number of pixels can be arranged to perform fast data scanning. In addition, the CIS consumes less power, that is approximately ⅕ of the power consumed by the CCD, and has a low manufacturing cost. Thus, a large-size CIS can be produced at a relatively low cost. The CIS can be manufactured on a chip using a process of fabricating MOSFETs or CMOS transistors, and thus signal processing circuits can be formed on the same chip while reducing the number of connecting lines. Moreover, the CIS can be operated with a voltage lower than the voltage driving the CCD, and its periphery circuits can be arranged on the same chip. This can reduce the size of the CIS. Accordingly, the CIS may be an important image sensing device as an alternative or replacement for the CCD solid state image sensing device in future digital video systems.
A CIS type solid state image sensing device is applied to a cellular phone camera, a digital still camera, and the like. Color image data (R, G and B data) output from the solid state image sensing device drives a display device such as a Liquid Crystal Display (LCD). In a system employing the CIS type solid state image sensing device, a sub-sampling mode of operation of the solid state image sensing device outputs a video signal with a reduced vertical resolution. The sub-sampling mode supports a high frame rate when a high-resolution display is not required, such as, for example, when a moving image display is displayed, an image to be captured is previewed, or automatic focus is set.
FIG. 1 is a block diagram of a conventional CIS type solid state image sensing device 100. Referring to FIG. 1, the conventional CIS type solid state image sensing device 100 includes an Active Pixel Sensor (APS) array 110, a row driver 120, and an analog-to-digital converter (ADC) 130. The row driver 120 receives a control signal from a row decoder (not shown) and the analog-to-digital converter 130 receives a control signal from a column decoder (not shown). The solid state image sensing device 100 further includes a controller (not shown) generating timing control signals and addressing signals for outputting a selected and sensed video signal of each pixel. In the solid state image sensing device 100, in general, a color filter is arranged on each of the pixels constructing the APS array 110 such that only light having a specific color is output from the pixels. To construct color signals, at least three kinds of color filters are arranged on the APS array 110. The most general color filter array has a Bayer pattern in which red and green color patterns are arranged in one row and green and blue color patterns are arranged in another row. Here, the green color pattern, which is closely related to a luminance signal, is arranged in all rows and the red and blue color patterns are alternately arranged in the rows to improve luminance resolution. A CIS having more than one million pixels is applied to a digital still camera in order to improve resolution.
In the CIS type solid state image sensing device 100, the APS array 110 senses light using photodiodes and converts the sensed light into electric signals to generate video signals. The video signals output from the APS array 110 include red (R), green (G) and blue (B) analog signals. The analog-to-digital converter 130 receives the analog video signals output from the APS array 110 and converts the analog video signals into digital signals.
In the conventional CIS type solid state image sensing device 100 shown in FIG. 1, the analog-to-digital converter 130 converts the video signals sensed by the photodiodes into digital signals using a Correlated Double Sampling (CDS) method, which is disclosed in U.S. Pat. No. 5,982,318 and U.S. Pat. No. 6,067,113. CDS analog-to-digital conversion is divided into a step of receiving reset signals from the APS array 110 and a step of receiving video signals sensed by the photodiodes to convert the video signals into digital signals.
FIG. 2 is a circuit diagram of a Correlated Double Sampling (CDS) unit 160 for each column, which is included in the analog-to-digital converter 130 of FIG. 1. Referring to FIG. 2, whenever the photodiodes of the APS array 110 newly sense light at a predetermined period, the APS array 110 outputs a reset signal VRES to the CDS unit 160 before the photodiodes output a newly sensed video signal VSIG to the CDS unit 160. A column CDS circuit 131 amplifies a difference between the reset signal VRES and the video signal VSIG using a ramp signal VRAMP. Referring to FIG. 3, switches S1, S2, S3 and S4 in the CDS circuit 131 are all turned on and the reset signal VRES is input to the column CDS circuit 131 at the instant of time (1). At the instant of time (2), only the switches S1 and S2 are turned on and the sensed video signal VSIG is input to the column CDS circuit 131. At the instant of time (3), all the switches S1, S2, S3 and S4 are turned off and the ramp signal VRAMP is activated. Accordingly, the difference between the reset signal VRES and the video signal VSIG, stored in capacitors C1 and C2, is increased as the ramp signal VRAM is increased. An output signal OUT, which is activated when the increased difference exceeds a predetermined reference level, is generated by amplifiers AMP1 and AMP2. Here, the instant of time when the output signal OUT is activated is delayed as the difference between the reset signal VRES and the video signal VSIG is increased.
The output signal OUT of the column CDS circuit 131 is converted into a digital value proportional to its pulse width in a predetermined circuit. The converted digital signal is interpolated in a subsequent processor and drives a display device such as an LCD.
When the CIS solid state image sensing device captures a still image, video signals of all pixels, sensed by the photodiodes of the APS array 110, are output. In the sub-sampling mode, however, the video signals are output with reduced resolution. In the case of a CIS type solid state image sensing device having an APS array with Super extended Graphic Adapter (SXGA) resolution, for example, the solid state image sensing device outputs SXGA-grade video signals when it photographs a still image. However, the solid state image sensing device outputs Video Graphics Adapter (VGA)-grade video signals in sub-sampling mode operations including a moving picture display operation, a preview operation and an automatic focusing operation. For reference, the number of pixels of SXGA resolution is 1280×1024 and the number of pixels of VGA resolution is 640×480. In a typical example, even a CIS type solid state image sensing device having an APS array with Ultra extended Graphics Adapter (UXGA) resolution outputs video signals with less than VGA-grade resolution in the sub-sampling mode to reduce the quantity of processed data. For reference, the number of pixels of UXGA resolution is 1600×1200.
In the sub-sampling mode of the conventional CIS type solid state image sensing device 100, only video signals of a specific row and column arranged at a predetermined interval are output to the analog-digital converter 130 to reduce vertical resolution. To decrease SXGA resolution to VGA resolution, for instance, only data corresponding to the intersection of one row and one column is selected from pixel data corresponding to two rows and two columns and other data are removed such that resolution is reduced by half. When only data corresponding to one row and column are selected from data corresponding to many rows and columns, the resolution can be further reduced and thus the quantity of processed data can be further decreased.
Unfortunately, there also exists a video signal VSIG that is not used, but discarded, in the sub-sampling mode of the conventional CIS type solid state image sensing device 100. This increases the Signal to Noise Ratio (SNR) distortion and causes aliasing that does not smoothly display oblique lines on a display.